datasheet, circuit, data sheet: HITACHI – 4-bit D-type site for Electronic Components and Semiconductors, integrated circuits, diodes. datasheet, pdf, data sheet, datasheet, data sheet, pdf, Hitachi Semiconductor, 4-bit D-type Register (with 3-state Outputs). Quad D-type flip-flop; positive-edge trigger; 3-state. PDF datasheet. OE1, 1 •, 16, Vcc. OE2, 2, 15, MR. Q0, 3, 14, D0. Q1, 4, 13, D1. Q2, 5, 12, D2.
| Author: | Dijas Duzil |
| Country: | Iran |
| Language: | English (Spanish) |
| Genre: | History |
| Published (Last): | 1 June 2012 |
| Pages: | 449 |
| PDF File Size: | 11.35 Mb |
| ePub File Size: | 16.90 Mb |
| ISBN: | 879-9-82470-448-5 |
| Downloads: | 93475 |
| Price: | Free* [*Free Regsitration Required] |
| Uploader: | Faekazahn |
Output Enable Control inputs. The data outputs change state on the positive going edge of the clock.
When both Data Enable Controls are low, data at the D inputs are loaded into the flip—flops with the rising edge of the Clock input. The outputs are placed in the 3-stage mode when either 74137 the output disable pins are in the logic high level. Clearing is enabled by taking the clear input to a logic high level. When either M or N datasjeet both is are high the output is disabled to the high-impedance state; however sequential operation of the flip-flops is not affected.
Data on these pins, when enabled by the Data—Enable Controls, are entered into the flip—flops on the rising edge of the clock.
When either or both of these controls are high, there datassheet no change in the state of the flip—flops, regardless of any changes at the D or Clock inputs. When either or both of the Output Enable Controls are high, the Q outputs of the device are in the high—impedance state.
Datasheet pdf – 4-bit D-type Register (with 3-state Outputs) – Hitachi Semiconductor
Data on these pins, when enabled by the. During normal operation of the.
When both controls are. Output Enable Controls are high, the Q outputs of the device. The 3-state outputs allow the. During 3—state operation, these outputs assume a high—. During 3—state operation, these outputs assume a high— impedance state. The 3-state outputs allow the device to be used in bus organized systems.
Clearing is enabled by taking the clear input to a logic. A high level on this pin resets all flip—flops and forces the Q outputs low, if they are not already in high—impedance state. Data—Enable Controls, are entered into the flip—flops on the. During normal operation of the device, the outputs of the D flip—flops appear at these pins.
(PDF) 74173 Datasheet download
If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs. The input disable allows the flip-flops to remain in their present states without having to disrupt the clock.
The four D type Flip-Flops operate synchronously from a common clock. Enable Controls are low, data at the D inputs are loaded into. When either M or N or both is are high the output is disabled to the high-impedance state. The outputs are placed in the 3-stage mode when either of the. When either or both of the. Home – IC Supply – Link. If either of the 2 input disables are taken to a logic high level, the Dstasheet outputs are fed back to the inputs, forcing the flip-flops to remain in the same state.
When both controls are low, the device outputs display the data in the flip—flops. Home – IC Supply – Link. Active—low Data Enable Control inputs. A high level on this pin resets all.